S. Sadana, M Gupta, R. Shankar , S. Singla, H.S. Jatana and U. Ganguly, “Demonstration of Charge Trap Flash Bit-Cell in 180nm CMOS Logic Foundry” ICEE 2018
V. Bhatt, S. Shrivastava, T. Chavan and U. Ganguly, “Software-Level Accuracy Using Stochastic Computing With Charge-Trap-Flash Based Weight Matrix” IJCNN 2020
S. Shrivastava, T. Chavan, V. Bhatt, U. Ganguly “Flash Memory for Low Energy Synapse ” (Application Number 201921006118)
Shalini Shrivastava, Tanmay Chavan, Udayan Ganguly, “Ultra-low Energy charge trap flash based synapse enabled by parasitic leakage mitigation