Leakage currents dominate the overall energy consumption of circuits with long idle times. Portable devices like smartphones, tablets, wearable devices, medical implants, and sensor nodes have tremendous constraints on their energy consumption. Power Gating remains as one of the dominant method of leakage current reduction. For the first time, PG switch is biased in the super turn-off and the super turn-on mode during the off-state and the on-state, respectively. A simple switched-capacitor network reconfigures and biases the PG switch in four different possible states with low area and power overhead. During the super turn-off, voltage stress is avoided in the PG switch when the circuit load uses supply voltage equal to the nominal VDD in a given technology, and maximum possible leakage current reduction is achieved by the optimal biasing of the gate voltage. The proposed SwCap PG is experimentally validated in the 180nm CMOS technology. Measurement results of CMOS SwCap PG show that leakage current and RON reduce by 186-226× and 18% respectively, as compared to the conventional PG.