Low-power and low-area neurons are essential for hardware implementation of large-scale SNNs. Various novel-physics-based leaky-integrate-and-fire (LIF) neuron architectures have been proposed with low power and area, but are not compatible with CMOS technology to enable brain scale implementation of SNN. In this project we aim to develop a CMOS compatible ultra energy efficient and compact leaky-integrate-and-fire (LIF) neuron. Capacitor requirement for integration is one of the major challenges in CMOS compatible neurons. We aim to exploit band-to-band-tunneling (BTBT) based neurons for low-power, low-area, and low-leakage neuron development. The next challenge is to develop a compact low-power thresholding circuit to fully implement the LIF neuron.